The implementation of a silicon germanium (SiGe) channel has some notable advantages over a traditional silicon (Si) channel. For instance, a SiGe channel provides a desirable threshold voltage (pVt) without the need for band edge workfunction metal. A SiGe channel also has improved negative-bias temperature instability (NBTI) as compared to Si, which allows for further inversion-layer thickness (Tiny) scaling. A SiGe channel also has higher hole mobility as compared to Si. All of these factors lead to performance improvements over a typical Si-based channel.
However, a notable performance challenge is that the interface charge density (Dit) at the gate dielectric can be more than an order of magnitude greater for a SiGe channel as compared to Si. For instance, Dit on Si is typically in the 1×1010 cm2 range, whereas Dit can be in the range of 1×1011 cm2 to 1×1012 cm2 for SiGe.
Therefore, techniques for reducing Dit for a SiGe channel (e.g., to the 1×1010 cm2 range) would be desirable.